The isolation of devices on a semiconductor substrate is important because improper device isolation can cause current leakage that consumes significant amounts of power. In addition, improper device isolation can cause latch-up that momentarily or permanently damages circuit functions. Still further, improper device isolation can degrade noise margins, shift voltages, or cause crosstalk in an integrated circuit (IC).
A conventional LOCOS (local oxidation of silicon) device isolation process includes ion-implantation for channel stops and growth of thick field oxide regions that laterally isolate the active device regions of an IC. For ion implantation and oxide growth, the LOCOS process typically uses a mask including a silicon nitride layer and an underlying pad oxide that are patterned to cover the active device regions. The pad oxide layer releases stress that the silicon nitride layer causes during the LOCOS process. Resulting LOCOS isolation structures have some drawbacks. In particular, lateral oxidation of the silicon under the silicon nitride mask makes the edge of each field oxide region resemble the shape of a bird's beak, and the lateral diffusion of channel-stop dopants causes the dopants to encroach into the active device regions. These effects increase transistor threshold voltages, reduce current driving capabilities, and reduce active device areas. Therefore, the effects can be serious problems when devices are scaled down for very large scale integration (VLSI).
An isolation technique using shallow trenches has been developed in an attempt to avoid the drawbacks of the LOCOS isolation structure. Generally, the shallow trench isolation (STI) fabrication process includes depositing a silicon nitride layer over a semiconductor substrate, for example, using low pressure chemical vapor deposition (LPCVD) with a flow of dichlorosilane (SiH.sub.2 Cl.sub.2, hereinafter referred to "DCS") and armmonia (NH.sub.3) in a ratio of 1:10. The silicon nitride layer is then patterned, and etching of exposed portions of the semiconductor substrate forms trenches. A trench filling insulating layer is then deposited over the semiconductor substrate, before a high temperature annealing process removes defects resulting from etching the semiconductor substrate and depositing the insulating layer.
Undesirably, this trench isolation process applies a residual tensile stress of about 1.3.times.10.sup.10 dyne/cm.sup.2 or more to the active region of the semiconductor substrate during the high temperature annealing. The stress can cause a dislocation defect. Such a defect reduces reliability of the gate oxide layers and degrades refresh characteristics in memory circuits such as dynamic random access memories (DRAMs). To address the problem of stress, silicon rich nitride layers exhibiting low residual tensile stress can be employed as an etch mask for trench formation. However, to form a silicon rich nitride layer exhibiting stress that is less than 3.times.10.sup.9 dyne/cm.sup.2, the flow ratio of DCS to NH.sub.3 must be larger than 5 to 1. FIG. 1 shows the relationship between the residual tensile stress of the silicon nitride layer and the reactant gas flow ratio of DCS to NH.sub.3. The large quantity of DCS introduced to form the desired silicon rich nitride also forms unacceptably large quantities of particles (typically NH.sub.4 Cl) from reactions between NH.sub.3 and decomposition by-products of DCS, i.e., HCl.
HCl is not formed if SiH.sub.4 (silane) is the silicon source gas instead of the DCS, but SiH.sub.4 causes other problems. With SiH.sub.4, decreasing the in-wafer uniformity of a nitride layer down to less than 5% is difficult, and the number of wafers that can be processed per batch decreases due to different uniformities of nitride layers on different wafers. Improving batch uniformity requires increasing the temperature slope in the reacting chamber, which results in variations in characteristics of the nitride layer, thereby affecting wet and dry etching rates of the nitride layer.